Q. Assertion (A): ECL gate has very high speed of operation.

Reason (R): Transistors in ECL do not go into saturation region.

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Q. A half adder adds

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Q. The no. of comparators required in a 3 bit comparator type ADC is

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Q. If the ladder reference voltage is 2 V, then minimum comparator resolution required is

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Q. In a 7 segment LED display, the minimum number of segments is activated when the input decimal number is

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Q. A 10 bit ADC with a full scale output voltage of 10.24 V is to be designed to have ± LSB/2 accuracy. If ADC is calibrated at 25°C, the maximum net temperature coefficient of ADC should not exceed

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Q. If all the LEDs in a seven segment display are turned on, the number displayed is

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Q. In a three input AND gate A = 1, B = 1, C = 0 The output Y =

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Q. DeMorgan's first theorem shows the equivalence of

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Q. 0.1011₂ = __________ .

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Q. A 4 bit down counter starts counting from 1111 irrespective of modulus.

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Q. The number of counter states which an 8 bit stair step A/D converter has to pass through before conversion takes place is equal to

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Q. 74 HC series can sink upto 4 mA. The 74 LS series has IIL(max) - 0.4 mA. How many 74 LS inputs be driven by 74 HC output?

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Q. An 8 bit transistor register has output voltage of low-high-low-high-low-high-low-high. The decimal number stored is

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Q. The number of cells in a 4 variable K map is

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Q. In which counter does the maximum frequency depend on the modulus?

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Q. A current tracer responds to

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Q. A presettable counter with 4 flip flops can start counting from

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Q. A logical expression Y = A + A̅B is equal to

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Q. Using the same flip flops

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