Q. In figure, ID = 4 mA. Then VDS =

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Q. In figure, V0 =

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Q. In the circuit of figure diode will conduct

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Q. In figure, V0 =

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Q. The JFET in the circuit shown in figure has an IDSS = 10 mA and Vp = -5V. The value of the resistance Rs for a drain current IDS = 6.4 mA is

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Q. In figure, V0 =

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Q. In the op-amp circuit of figure, V0 =

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Q. In figure the zener has a resistance of 5 ohms. As the load resistance is varied, the output voltage

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Q. The transistor of following figure in Si diode with a base current of 40 μA and ICBO = 0, if VBB = 6V, RE = 2 kΩ and β = 90, IBQ = 20 μA then IEQ =

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Q. In the CE circuit shown in figure the slope of ac load line will be

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Q. The op-amp circuit shown in the figure is a filter. The type of filter and its cut off type of filter and its cut off frequency are respectively.

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Q. In the circuit of figure, PIV can be up to

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Q. In the circuit of figure β = 50 and VBE = 0.5 V. The quiescent value of base current IB is

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Q. In figure the input and output Miller capacitances are

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Q. Figure uses 10 V zener diode. The minimum and maximum current through series resistance are

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Q. When Z1 << Z, The circuit of figure works as

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Q. Voltage VL in the circuit when Vs < 0 where D is an ideal diode. (Take R1 = Rs = RL = 1 Ω)

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Q. For the amplifier in figure, β = 800. The mid-band voltage gain V0/Vi is

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Q. In the circuit of figure, v0 =

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Q. The bandwidth of an amplifier is BW, of n-stage of such as amplifier are cascaded, the bandwidth will become

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