Q. The input to a parity detector is 1001. The output is

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Q. A 4 bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to

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Q. As the number of flip flops are increased, the total propagation delay of

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Q. In a 4 input OR gate, the total number of High outputs for the 16 input states are

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Q. If A is 1011, A" is

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Q. Which of the following is not a characteristic of a flip flop?

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Q. The number of flip flops needed for a Mod 7 counter are

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Q. For AB + A̅C + BC = AB + A̅C the dual form is

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Q. A DAC has full scale output of 5 V. If accuracy is ± 0.2% the maximum error for an output of 1 V is

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Q. Binary number 1101101101 is equal to decimal number

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Q. A 16:1 multiplexer has 4 select input lines.

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Q. Which one of the following can be used as parallel to series converter?

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Q. What will be conversion time of a successive approximation A/D converter which uses 2 MHz clock and 5 bit binary ladder containing 8 V reference.?

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Q. A + A . B =

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Q. The device 'one shot' has

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Q. If number of information bits is 4, the parity bits in Hamming code are located at bit positions __________ from the LSB.

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Q. A certain JK FF has tpd = 12 n sec the largest MOD counter that can be constructed from these FF and still operate up to 10 MHz is

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Q. Logic analyser is

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Q. The function Y = A B̅ C̅ + AB C̅ + A B̅ C + A̅ BC is to be realized using discrete gates. The inputs available are A, B, C. We need a total of

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Q. A 10 bit D/A converter gives a maximum output of 10.23 V. The resolution is

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