Q. In a NAND SR latch S = R = 1. Then

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Q. A 4 bit binary adder has 4 full adders.

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Q. In floating point representation, the accuracy is

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Q. The PC contains 0450 H and SP contains 08D 6 H. What will be content of P and SP following a CALL to subroutine at location 02 AFH?

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Q. Assuming accumulator contain A 64 and the carry is set (1). What will register A and (CY) contain after ADI A4H?

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Q. In a monolithic IC, resistors are formed from

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Q. For wired AND connection we should use

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Q. A̅̅ + AB̅ =

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Q. The resolution of a 12-bit D/A converter using a binary ladder with + 10V as the full scale output will be

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Q. Assertion (A): Demorgan's first theorem replaces a NOR gate by bubbled AND gate.

Reason (R): Double complement of a variable equals the variable.

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Q. A flip-flop circuit is

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Q. Assertion (A): The use of 2's complement has simplified the computer hardware for arithmetic operations

Reason (R): 2's complement is obtained by adding 1 to 1's complement.

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Q. How many lines are there in address bus of 8085 μp?

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Q. Consider the following statements Timer 555 can be used as

1. monostable multivibrator
2. bistable multivibrator
3. astable multivibrator

Which of the above statements are correct?

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Q. Which is correct with respect to computer memory?

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Q. A 3 bit binary adder should use

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Q. For a depletion type NMOS, Vp = - 4 volts. For VGS = 0, 1D = 16 mA in the pinch off region of VDS. For VGS = - 2, the value of ID in the pinch off region of VDS is given by

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Q. The two outputs of RS flip-flop are

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Q. The sum of 1110101₂ and 11011₂ in decimal form will be

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Q. Binary 1111 when added to binary 11111, the result in binary is

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