Question

In a clocked NAND latch, race condition occur when

a.

R and S are high CLK is low

b.

R and CLK are high and S is low

c.

R, S, CLK are high

d.

R, S, CLK are low

Posted under Electronics and Communication Engineering

Answer: (c).R, S, CLK are high

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Q. In a clocked NAND latch, race condition occur when
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