Digital Electronics MCQs

Welcome to our comprehensive collection of Multiple Choice Questions (MCQs) on Digital Electronics, a fundamental topic in the field of Electronics and Communication Engineering. Whether you're preparing for competitive exams, honing your problem-solving skills, or simply looking to enhance your abilities in this field, our Digital Electronics MCQs are designed to help you grasp the core concepts and excel in solving problems.

In this section, you'll find a wide range of Digital Electronics mcq questions that explore various aspects of Digital Electronics problems. Each MCQ is crafted to challenge your understanding of Digital Electronics principles, enabling you to refine your problem-solving techniques. Whether you're a student aiming to ace Electronics and Communication Engineering tests, a job seeker preparing for interviews, or someone simply interested in sharpening their skills, our Digital Electronics MCQs are your pathway to success in mastering this essential Electronics and Communication Engineering topic.

Note: Each of the following question comes with multiple answer choices. Select the most appropriate option and test your understanding of Digital Electronics. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

So, are you ready to put your Digital Electronics knowledge to the test? Let's get started with our carefully curated MCQs!

Digital Electronics MCQs | Page 99 of 117

Discover more Topics under Electronics and Communication Engineering

Q981.
For a NOR SR latch the normal resting state of inputs is

a.

S = R = 1

b.

S = 0, R = 1

c.

S = 0, R = 0

d.

S = 1, R = 0

Discuss
Answer: (c).S = 0, R = 0
Q982.
Decimal 18.29 when converted int 10's complement will become

a.

81.7707

b.

81.700

c.

81.777

d.

81.077

Discuss
Answer: (a).81.7707
Q983.
The complement of Boolean expression AB (Bฬ… C + AC) is

a.

(Aฬ… + Bฬ…) + (B + Cฬ…) + (Aฬ… + Cฬ…)

b.

Aฬ… Bฬ… + (B + Cฬ…)(Aฬ… + Cฬ…)

c.

(Aฬ… + Bฬ…) + (B + Cฬ…) (Aฬ… + Cฬ…)

d.

none of the above

Discuss
Answer: (c).(Aฬ… + Bฬ…) + (B + Cฬ…) (Aฬ… + Cฬ…)
Q984.
The product of which of the following gives the figure of merit of a logic family?

a.

Gain and bandwidth

b.

Propagation delay time and power dissipation

c.

Fan-out and propagation delay time

d.

Noise margin and power dissipation

Discuss
Answer: (b).Propagation delay time and power dissipation
Q985.
A JK flip flop can be converted to D flip flop by

a.

Connecting both J and K terminals to D

b.

Connecting J terminal to D and leaving K open

c.

Connecting K terminal to D and leaving J open

d.

Connecting J terminal to D and K terminal to D through an inverter

Discuss
Answer: (d).Connecting J terminal to D and K terminal to D through an inverter
Q986.
In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

a.

1101

b.

1001

c.

0101

d.

0001

Discuss
Answer: (a).1101
Q987.
Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

a.

Both A and R are correct and R is correct explanation of A

b.

Both A and R are correct but R is not correct explanation of A

c.

A is true, R is false

d.

A is false, R is true

Discuss
Answer: (b).Both A and R are correct but R is not correct explanation of A
Q988.
A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

a.

6M bands/s

b.

12M bands/s

c.

6 M bits/s

d.

12M bits/s

Discuss
Answer: (a).6M bands/s
Q989.
Assertion (A): An SR latch has the problem of RAC condition

Reason (R): While designing a digital circuit RAC condition should be avoided.

a.

Both A and R are correct and R is correct explanation of A

b.

Both A and R are correct but R is not correct explanation of A

c.

A is true, R is false

d.

A is false, R is true

Discuss
Answer: (b).Both A and R are correct but R is not correct explanation of A
Q990.
In a clocked NAND latch, race condition occur when

a.

R and S are high CLK is low

b.

R and CLK are high and S is low

c.

R, S, CLK are high

d.

R, S, CLK are low

Discuss
Answer: (c).R, S, CLK are high
Page 99 of 117