Q. 1111 + 11111 =

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Q. If one wants to design a binary counter, preferred type of flip-flop is

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Q. (100101)₂ is

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Q. Race condition occurs in

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Q. Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is

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Q. Which of the following is a self-complementing code?

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Q. ALU processes

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Q. For an N bit ADC, the percentage resolution is [1/2ᴺ - 1)] 100.

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Q. Commercial ECL gates use two ground lines and one negative supply to

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Q. Dynamic memory cells are constructed using

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Q. Which of the following is incorrect?

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Q. In which function is each term known as maxterm?

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Q. For a NOR SR latch the normal resting state of inputs is

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Q. Decimal 18.29 when converted int 10's complement will become

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Q. The complement of Boolean expression AB (B̅ C + AC) is

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Q. The product of which of the following gives the figure of merit of a logic family?

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Q. A JK flip flop can be converted to D flip flop by

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Q. In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

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Q. Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

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Q. A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

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