Q. For a NOR SR latch the normal resting state of inputs is

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Q. Decimal 18.29 when converted int 10's complement will become

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Q. The complement of Boolean expression AB (B̅ C + AC) is

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Q. The product of which of the following gives the figure of merit of a logic family?

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Q. A JK flip flop can be converted to D flip flop by

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Q. In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

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Q. Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

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Q. A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

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Q. Assertion (A): An SR latch has the problem of RAC condition

Reason (R): While designing a digital circuit RAC condition should be avoided.

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Q. In a clocked NAND latch, race condition occur when

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Q. In Von-Neumann-or Princeton-type computers, the program

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Q. In a digital system there are three inputs ABC. Output should be high when atleast two inputs are high. Then output =

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Q. Which of them radiates emission?

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Q. Which multivibrator can be used as a clock timer?

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Q. T-flip-flop is commonly used as

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Q. In the NMOS inverter

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Q. Assuming accumulator contain A 64 and the carry is set (1).What will register A and (CY) contain after RAR?

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Q. A decade counter

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Q. The range of signed decimal number that can be represented by 6 bit in complement number is

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Q. Schottky clamping is resorted to in TTL gates

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