Q. A gate in which shift register is connected as shown in the figure below. How many clock pulse (after reset to '0') the contents of the shift register are '000' again?

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Q. For the K map of the given figure the simplified Boolean expression is

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Q. Figure shows three pulse train inputs to a 3-input AND gate. Assuming positive logic, the output signal obtained in figure would be

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Q. A 12-bit binary counter has the following state. The octal number represented is

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Q. For the K map of the given figure the simplified Boolean expression is

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Q. A clock pulse is fed into 3 bit binary down count. The signal at B output is

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Q. The boolean expression for shaded area in the given figure is

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Q. The given figure shows a K-map for a Boolean function. The number of essential prime implicants is

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Q. For the logic circuit given, what is the simplified Boolean function?

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Q. The accuracy of A/D conversion is generally

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Q. Consider the following statements in connection with CMOS inverter in figure where both the MOSFET are of enhancement type and both have a threshold voltage of 2 V

statements 1: T1 conducts when vi ≥ 2 V
statements 2: T1 is always in saturation when v0 = 0 V

Which of the following is correct?

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Q. In number system e.g. 6, a “decade” counter has to recycle to 0 at the sixth count. Which of the connections indicate below will realize this resetting? (a logic “0” at the R inputs resets the counters)

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Q. The logic realized by the circuit shown in figure

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Q. The contents of stack location after the call operation will be

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Q. In figure, R = 20KΩ and C = 75 pF. The converter clock frequency will be

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Q. In the switching circuit, switches A, B have value 0 for OFF, 1 for ON and the output Y has 0 volts for 1 volts, then the expression for Y is

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Q. The output Y of the circuit shown in the figure is

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Q. What is the result for following expression (map method)?

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Q. The MOS symbols shown indicates:

1. that it is depletion type
2. that it is enhancement type
3. that it is n channel
4. that it is p channel
5. that electrons flow from D to S
6. that holes flow from D to S

The only true statements are

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Q. For the logic circuit of the given figure the simplified Boolean expression is

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