Q. Assertion (A): Master slave JK flip flop is commonly used in high speed synchronous circuitry

Reason (R): Master slave JK flip flop uses two JK flip flops in cascade.

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Q. ECL is a saturating logic.

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Q. The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be

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Q. 9's complement of 12₁₀ is

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Q. The minterm designation for ABCD is

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Q. Read the following statements

1. The circuitry of ripple counter is more complex than that of synchronous counter.
2. The maximum frequency of operation of ripple counter depends on the modulus of the counter.
3. The maximum frequency of operation of synchronous counter does not depend on the modulus of the counter.

Which of the above statements are correct?

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Q. An equivalent 2's complement representation of the 2's complement number 1101 is

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Q. In a 7 segment display the segments a, c, d, f, g are lit. The decimal number displayed will be

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Q. The minimum number of comparators required to build an 8 bit flash ADC is

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Q. For a Mod-64 synchronous counter the number of flip flops and AND gates needed is

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Q. A 4 bit DAC gives an output of 4.5 V for input of 1001. If input is 0110, the output is

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Q. Boolean expression for the output of XNOR (Equivalent) logic gate with inputs A and B is

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Q. An SR flip flop can be built using NOR gates or NAND gates.

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Q. A 14 pin NOT gate 1C has __________ NOT gates.

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Q. F's complement of (2BFD)hex is

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Q. A 4 bit ripple counter uses flip flops with propagation delay of 50 ns each. The maximum clock frequency which can be used is

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Q. An AND gate has two inputs A and B and one inhibit input S. Out of total 8 input states, output is 1 in

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Q. 268₁₀ = __________ .

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Q. In a JK Master slave flip flop

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Q. A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be

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