Q. The minimized version of logic circuit in the given figure is

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Q. In the given figure shows a negative logic AND gate. If positive logic is used this gate is equivalent to

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Q. The Boolean function/implemented in the figure using two I/P multiplexers is

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Q. For the logic circuit of the given figure the simplified Boolean equation

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Q. In the given figure RC = RL = 1 kΩ, then V0 =

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Q. Inputs A and B of the given figure are applied to a NAND gate. The output is LOW

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Q. For the NMOS gate in the given figure, F =

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Q. The logic circuit of the given figure is equivalent to

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Q. In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is

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Q. The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is

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Q. In the figure, the LED

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Q. Four inputs A, B, C, D are fed to a NOR gate. The output of NOR gate is fed to an inverter. The output of inverter is

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Q. The circuit in the figure is has two CMOS-NOR gates. This circuit functions as a

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Q. In the TTL circuit in the figure, S₂ to S₀ are select lines and X₇ to X₀ are input lines. S₀ and X₀ are LSBs. The output Y is

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Q. The Boolean expression for the shaded area in the Venn diagram is

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Q. The logic realized by the circuit shown in figure below is

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Q. The inputs A and B of the given figure are applied to a two input NOR gate. The output waveform is

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Q. In the circuit of the given figure, V₀ =

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Q. In following figure, the initial contents of the 4-bit serial in parallel out, right shift, shift register as shown in figure are 0110. After 3 clock pulses the contents of the shift register will be

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Q. For the logic circuit of the given figure, the minimized expression is

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