Q. In the circuit of the given figure, V₀ =

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Q. In following figure, the initial contents of the 4-bit serial in parallel out, right shift, shift register as shown in figure are 0110. After 3 clock pulses the contents of the shift register will be

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Q. For the logic circuit of the given figure, the minimized expression is

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Q. The inputs to a NAND gate are as shown in the given figure. The waveform of output is

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Q. In the given figure A = 1, B = 1. B is now changed to a sequence 101010................The outputs X and Y will be

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Q. In 8085 microprocessor, what are the contents of register SP, after the interrupt has been started?

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Q. To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the ground is

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Q. A gate in which shift register is connected as shown in the figure below. How many clock pulse (after reset to '0') the contents of the shift register are '000' again?

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Q. For the K map of the given figure the simplified Boolean expression is

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Q. Figure shows three pulse train inputs to a 3-input AND gate. Assuming positive logic, the output signal obtained in figure would be

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Q. A 12-bit binary counter has the following state. The octal number represented is

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Q. For the K map of the given figure the simplified Boolean expression is

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Q. A clock pulse is fed into 3 bit binary down count. The signal at B output is

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Q. The boolean expression for shaded area in the given figure is

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Q. The given figure shows a K-map for a Boolean function. The number of essential prime implicants is

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Q. For the logic circuit given, what is the simplified Boolean function?

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Q. The accuracy of A/D conversion is generally

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Q. Consider the following statements in connection with CMOS inverter in figure where both the MOSFET are of enhancement type and both have a threshold voltage of 2 V

statements 1: T1 conducts when vi ≥ 2 V
statements 2: T1 is always in saturation when v0 = 0 V

Which of the following is correct?

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Q. In number system e.g. 6, a “decade” counter has to recycle to 0 at the sixth count. Which of the connections indicate below will realize this resetting? (a logic “0” at the R inputs resets the counters)

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Q. The logic realized by the circuit shown in figure

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