Q. A . 0 =

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Q. The number of memory locations in which 14 address bits can access is

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Q. What will be conversion rate for a counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time

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Q. A 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. It meets standard linearity then resolution in percent and volts.

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Q. What will be output for decimal input 82?

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Q. Assertion (A): The access time of memory is lowest in the case of DRAM

Reason (R): DRAM uses refreshing cycle.

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Q. In a 3 input NOR gate, the number of states in which output is 1 equals

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Q. Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is needed to interconnect them

Reason (R): VOH, VOL, VIH and VIL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V. VIL and VIH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively.

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Q. The series 54 H/74 H denotes

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Q. For a 4096 x 8 EPROM, the number of address lines is

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Q. Assertion (A): A PROM can be used as a synchronous counter

Reason (R): Each memory location in a PROM can be read synchronously.

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Q. A̅ B̅ C̅ D̅ + (A̅B̅) C D̅ =

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Q. Find the output voltage for 011100 in a 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V.

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Q. Binary number 1101 is equal to octal number

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Q. The complement of exclusive OR function is

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Q. Decimal -90 equals __________ in 8 bit 2s complement

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Q. 23.6₁₀ = __________ ₂

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Q. In a shift left register, shifting a bit by one bit means

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Q. A multiple emitter transistor has many emitters and collectors.

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Q. A mode-10 counter can divide the clock frequency by a factor of

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